The present invention relates generally to integrated circuit testing, and more particularly to a method and apparatus for non-contact testing and diagnosing of inaccessible shorted integrated circuit connections.
During the manufacture of circuit assemblies such as printed circuit boards (PCBs), multi-chip modules (MCMs), or other packaging hierarchies, testing for interconnection defects such as open and shorted joints or interconnects is performed. Well-known capacitance lead-frame sensing technologies exist that can detect opens between the pins of an integrated circuit (IC) and the mounting substrate (typically a printed circuit board). Typical implementation of capacitive probe assemblies that implement a capacitive sensor may be found in the following references, each of which is incorporated herein by reference for all that it teaches: U.S. Pat. No. 5,498,964, to Kerschner et al., entitled “Capacitive Electrode System for Detecting Open Solder Joints in Printed Circuit Assemblies”, U.S. Pat. No. 5,124,660 to Cilingiroglu, entitled “Identification of Pin-Open Faults By Capacitive Coupling Through the Integrated Circuit Package”, U.S. Pat. No. 5,254,953 to Crook et al., entitled “Identification of Pin-Open Faults By Capacitive Coupling Through the Integrated Circuit Package”, and U.S. Pat. No. 5,557,209 to Crook et al., entitled “Identification of Pin-Open Faults By Capacitive Coupling Through the Integrated Circuit Package”.
U.S. patent application Ser. No. UNKNOWN, entitled “Methods And Apparatus For Non-Contact Testing And Diagnosing Open Connections” to Parker et al., filed on Apr. 28, 2004, and assigned to the assignee of interest herein provides a method for testing for open power and ground connections in connectors and sockets, by making use of the inherently available coupling capacitors that exist between connector pins. When a signal pin is tested that is coupled to a nearby ground pin, an open on that ground pin will cause the signal pin measurement to rise in value.
For better understanding of the invention, a brief introduction to capacitive lead frame testing techniques is now presented. Turning to the drawings, FIG. 1A is a cross-cut side view of a basic test setup 10a for testing for open signal pins on an integrated circuit using conventional capacitive lead-frame testing techniques. As shown in FIG. 1, the test setup 10a includes a signal source 22, which supplies an alternating current (AC) signal, typically eight kiloHertz (8 KHz) at one hundred twenty millivolts (120 mV). The output of signal source 22 is connected to a tester probe 21a which connects to a node 41a of a printed circuit board 40. When a joint under test 35a is properly electrically connected to the node 41a of the printed circuit board 40, as shown in FIG. 1A, the output of the signal source 22 will also be electrically connected to the joint under test 35a. To reduce the effects of stray capacitive coupling between the joint under test 35a and respective neighboring joints, which interferes with the measurement of the joint under test, all neighboring joints 35b, 35c, 35d not being currently tested are preferably guarded by grounding them to the circuit ground 23.
The tester 20 includes a measuring device 24, such as an ammeter, a voltmeter, or other computing means which can be used to compute effective capacitance. The measuring device 24 is connected to a capacitive test probe 28 which comprises a receiver buffer 25 electrically coupled to a sense plate 26 of the capacitive test probe 28. The capacitive test probe 28 is placed on top of the integrated circuit package 31. A thin dielectric (not shown) may be placed between the integrated circuit package 31 and the sense plate 26 of the capacitive test probe 28. The capacitive test probe 28 is connected to a measuring device 24, such as an ammeter, a voltmeter or computing means to compute the effective capacitance.
When the test is performed, the signal source 22 is activated and applied to node 41a on the printed circuit board 40 which should be attached to the integrated circuit lead 34a by joint under test 35a. The source signal should then pass from the joint under test 35a to the lead 34a of the integrated circuit package 31. Through capacitive coupling between the lead 34a (which forms a plate) and sense plate 26 of the capacitive test probe 28, the signal is passed to the receiver buffer 25 of the capacitive test probe 28 and then to the measuring device 24. If the measured parameter falls within predetermined limits, then the joint under test 35a is connected to the node 41a of the printed circuit board 40. If the joint under test 35a is not connected to the node 41a of the printed circuit board 40 or if the conductive path between the output of the signal source 22 and node 41a is broken, a smaller signal will be conducted to the capacitive test probe 28 and the threshold level of the signal will not be measured by the measuring device 24, indicating that an open fault is present.
FIG. 1B is a schematic diagram illustrating the equivalent circuit 10b of the test setup 10a of FIG. 1A. As shown therein, the signal source 22 and measuring device 24 are commonly connected to a circuit ground 23. A sense capacitance (Csensor) is formed between the sense plate 26 of the capacitive test probe 28 and the lead frame 34a to which the joint under test 35a is connected. If the joint under test 35a is not properly connected to the node 41a of the printed circuit board 40 (as represented in the model 10a with switch 12 open), a joint capacitance Cjoint is formed between the lead frame 34a and node 41a. If, however, the joint under test 35a is properly electrically connected to the node 41a (as represented in the model 10a with switch 12 closed), no joint capacitance Cjoint is formed.
It can be determined from the equivalent circuit model 10b that the measured capacitance for a properly soldered (i.e., “good”) joint (where switch 12 is closed) is given by:CGOOD—JOINT=CSENSE,
and the measured capacitance for an open (i.e., “bad”) joint (where switch 12 is open) is given by:COPEN—JOINT=CSENSE*CJOINT/(CSENSE+CJOINT).
The difference between CGOOD—JOINT and COPEN—JOINT is measurable and the values of the calculated parameters CGOOD—JOINT and COPEN—JOINT can be used to classify joints as open or closed based on actual capacitively sensed measurements obtained from a device under test.
The above approaches focus on detection of open conditions between nodes of an integrated circuit device. However, defects that short nodes such as integrated circuit pins together are not typical applications of capacitive lead-frame testing. Most such defects are detected using standard shorts tests or Boundary-Scan approaches. However, it would be desirable to apply capacitive lead-frame technology to detection of shorts between nodes of an integrated circuit device when some of the nodes are inaccessible.